MBW=0, BIGEND=0, ISEL=0, RCNT=0, REW=0, CURPIPE=others
CFIFO Port Select Register
| CURPIPE | CFIFO Port Access Pipe Specification 0 (0000): DCP(Defaultcontrolpipe) 0 (others): Setting prohibited 1 (0001): Pipe1 2 (0010): Pipe2 3 (0011): Pipe3 4 (0100): Pipe4 5 (0101): Pipe5 6 (0110): Pipe6 7 (0111): Pipe7 8 (1000): Pipe8 9 (1001): Pipe9 |
| Reserved | This bit is read as 0. The write value should be 0. |
| ISEL | CFIFO Port Access Direction When DCP is Selected 0 (0): Reading from the buffer memory is selected 1 (1): Writing to the buffer memory is selected |
| Reserved | These bits are read as 00. The write value should be 00. |
| BIGEND | CFIFO Port Endian Control 0 (0): Little endian 1 (1): Big endian |
| Reserved | This bit is read as 0. The write value should be 0. |
| MBW | CFIFO Port Access Bit Width 0 (0): 8-bit width 1 (1): 16-bit width |
| Reserved | These bits are read as 000. The write value should be 000. |
| REW | Buffer Pointer Rewind 0 (0): The buffer pointer is not rewound. 1 (1): The buffer pointer is rewound. |
| RCNT | Read Count Mode 0 (0): The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.) 1 (1): The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO. |